1. Field of the Invention
The field of the present invention relates to a multi-stage semiconductor memory and the sensing of multi-level memory cell data; and in particular to a method and apparatus for sensing multi-level cell data in one read cycle.
2. Description of Related Art
In a conventional memory cell, one bit of data is stored per cell. Popular classes of non-volatile semiconductor memory devices such as ROM and flash memory, have been modified to store more than one bit of data in one cell. This is accomplished by storing more than two threshold voltages V.sub.t either through different voltage threshold implantation for devices such as a MROM or by programming in devices such as flash cells.
A draw back to the MLC approach is that there is increased difficulty in sensing the various threshold voltages. This compromises the speed of reading the data. Also, since a more complicated sensing circuit is required additional chip area to implement the sense amplifier is required, increasing the cost of manufacturing a MLC.
Representative prior art sensing methods are described in U.S. Pat. No. 5,721,701 to Ikebe et al. entitled "HIGH READ SPEED MULTIVALUED READ ONLY MEMORY DEVICE"; and U.S. Pat. No. 5,543,738 to Lee et al. entitled "MULTI-STAGE SENSE AMPLIFIER FOR READ-ONLY MEMORY HAVING CURRENT COMPARATORS". These approaches in the prior art for two bit per cell memory, require three word line voltage levels for sensing the four possible combinations of two bits. The three levels are achieved in one prior art approach by applying the three levels in a three step sequence to the word line in each read cycle, sensing the cell output for each of the three levels. This three step sequence is relatively slow. The three levels are achieved in another approach by a two step sequence applying a first fixed word line voltage, and followed by a lower word line voltage or a higher word line voltage depending on the outcome of sensing during the first step. The two step technique in the prior art overcomes the slowness of the three step technique, but adds complexity because of the logic required to control the word line voltage during the second step. Further, the two step sequences of the prior art is limited to a single order of sensing.
What is needed is a novel method and apparatus for fetching MLC data with a fixed word-line voltage for all bits in the MLC independent of the order in which the bits are sensed. What is also needed is a sensing circuit with reduced complexity and reduced cost.